Analysis of Multifin n-FinFET for Analog Performance at 30nm Gate Length
Date of Submission
15th Dec 2025
General Information:
|
| Year Of Paper Submission : 2016-17 |
| Type of Applicant : Faculty |
| Selected Course : PhD |
| Department of Applicant : EXTC |
| Class of Applicant : Faculty |
Applicants Details:
|
| Applicant Name : Reena Sonkusare |
Guide Details:
|
| Department of Guide No. 1 : Electronics Engineering |
| Name of First Guide : Dr. Surendra Rathod |
Paper Details:
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| Title of Paper : Analysis of Multifin n-FinFET for Analog Performance at 30nm Gate Length |
| Type of Paper : Conference |
| Type of Publication : International |
| Date Of Conference / Journal / Book :
2000-01-01 |
| Conference_Type : IEEE |
| Address of Host Institute : Coimbatore |
| Citation of Journal : DOI: 10.1109/CESYS.2016.7889956 |
